1. Field of the Invention
The present invention relates to a resin sealed semiconductor device for use in testing employed for measuring effects exerted upon electronic elements by mechanical stresses due to resin seal, and a method for evaluation of the mechanical stresses due to the resin seal.
2. Description of the Background Art
When manufacturing a semiconductor device using electronic elements with dimensions, materials and the like different from those of conventional ones, it is necessary to give a test to see if these electronic elements have desired performance or not. In such a case, electronic elements with dimensions, materials and the like different from those of conventional ones are formed on a semiconductor chip for use in testing, and a test is performed using these electronic elements. The semiconductor chip for use in testing is referred to as a TEG (Test Element Group) chip. The structure of a conventional TEG chip will be described referring to FIGS. 7, 8 and 9.
As shown in FIG. 7, the TEG chip 1 has electronic elements (not shown in FIG. 7) formed on a main surface of a silicon substrate 3.
The TEG chip 1 is affixed on a main surface of a die pad 5. Bonding pads 7 are formed on end portions of the main surface of the silicon substrate 3. There are external leads 11 in the vicinities of side portions of the TEG chip 1. The external lead 11 and the bonding pad 7 are electrically connected by a wire 9. A part of an external lead 11, silicon substrate 3, die pad 5, bonding pad 7 and wire 9 are encapsulated with resin 13.
FIG. 8 is a plan view of the TEG chip 1 shown in FIG. 7. Silicon substrate 3 is affixed to the main surface of the die pad 5. A plurality of bonding pads 7 are formed on the side portions of the main surface of the silicon substrate 3. There are a plurality of external leads 11 in the vicinities of the side portions of silicon substrate 3. External leads 11 and bonding pads 7 are electrically connected by wire 9.
The main surface of silicon substrate 3 is divided into a MOS field effect transistor forming region 15, a capacitor forming region 17, a diode forming region 19, and an interconnection forming region 21. The broken lines in FIG. 8 indicate boundaries of the respective forming regions. No broken lines exist on a main surface of an actual silicon substrate 3. A part of leads 11, silicon substrate 3, bonding pads 7, die pad 5 and wires 9 are encapsulated with resin 13.
FIG. 9 is an enlarged view of a part indicated by E in FIG. 8. The region designated by E is within the MOS field effect transistor forming region designated by 15 in FIG. 8.
MOS field effect transistors 23a, 23b and 23c are respectively formed in the main surface of the silicon substrate 3. A plurality of bonding pads 7 are formed at end portions of the main surface of silicon substrate 3.
MOS field effect transistor 23a is provided with an impurity region 25a and a gate electrode 27a. The impurity region 25a is formed in the main surface of silicon substrate 3. Gate electrode 27a extends over impurity region 25a. Impurity region 25a is divided into two regions by gate electrode 27a. One region of impurity region 25a and bonding pad 7 are electrically connected by an aluminum interconnection layer 29a. Gate electrode 27a and bonding pad 7 are electrically connected by an aluminum interconnection layer 29b. The other region of impurity region 25a and bonding pad 7 are electrically connected by an aluminum interconnection layer 29c. L.sub.1 designates a gate length of gate electrode 27a.
MOS field effect transistor 23b is provided with a gate electrode 27b and impurity region 25b. Impurity region 25b is formed on the main surface of silicon substrate 3. Gate electrode 27b extends over impurity region 25b. Impurity region 25b is divided into two region 25b and bonding pad 7 are electrically connected by an aluminum interconnection layer 29d. Gate electrode 27b and bonding pad 7 are electrically connected by an aluminum interconnection layer 29e. The other region of impurity region 25b and bonding pad 7 are electrically connected by an aluminum interconnection layer 29f. L.sub.2 designates a gate length of gate electrode 27b.
MOS field effect transistor 27c is provided with an impurity region 25c and a gate electrode 27c. Impurity region 25c is formed on the main surface of silicon substrate 3. Gate electrode 27c extends over impurity region 25c. Impurity region 25c is divided into two regions by gate electrode 27c. One region of impurity region 25c and bonding pad 7 are electrically connected by an aluminum interconnection layer 29g. Gate electrode 27c and bonding pad 7 are electrically connected by an aluminum interconnection layer 29h. The other region of impurity region 25c and bonding pad 7 are electrically connected by an aluminum interconnection layer 29i. L.sub.3 designates a gate length of gate electrode 27c.
Although the gate lengths of MOS field effect transistors 23a, 23b and 23c are different from each other, their materials, shapes or the like are identical. When manufacturing a semiconductor device using a MOS field effect transistor with gate length L.sub.1 in the case of there is no semiconductor device manufactured by using a MOS field effect transistor with gate length L.sub.1, various tests are performed for MOS field effect transistor 23a to evaluate a MOS field effect transistor with gate length L.sub.1. Alternatively, variation of MOS field effect transistor characteristics of different gate lengths may be examined by comparing the results of the same test with respect to MOS field effect transistors 23a, 23b and 23c.
Description about what kinds of tests are performed with respect to MOS field effect transistors will be given referring to FIG. 10. A gate of a MOS field effect transistor is designated with 31. A source of the MOS field effect transistor is designated with 33. A drain of the MOS field effect transistor is designated with 35. A positive electrode of power source 37a and gate 31 are electrically connected. A negative electrode of power source 37a and source 33 are electrically connected. One electrode of a voltmeter 39a and gate 31 are electrically connected. A positive electrode of a power source 37b and drain 35 are electrically connected. A negative electrode of a power source 37b and one electrode of a voltmeter 41 are electrically connected. Drain 35 and one electrode of a voltmeter 39b are electrically connected.
A gate voltage is measured using voltmeter 39a. A drain current is measured employing ammeter 41. A drain voltage is measured employing voltmeter 39b.
The semiconductor chip is encapsulated with resin. The purpose is to avoid semiconductor element characteristic degradation due to effect of exterior atmosphere. However, it is known that, if a semiconductor chip is encapsulated with resin, mechanical stresses due to resin shrinkage are applied to the semiconductor element, so that the electric characteristics of the semiconductor element is degraded. A TEG chip 1 is also encapsulated with resin 13 as shown in FIG. 7 to implement the same conditions as that of a semiconductor chip. Mechanical stresses are applied to the TEG chip 1 in the direction designated by arrows in FIG. 7.
The degradation of electric characteristics of a semiconductor element due to resin seal will be described referring to test results. FIG. 11 is a sectional view of a semiconductor element employed in this test. This semiconductor element is a MOS capacitor 67. MOS capacitor 67 is provided with a silicon substrate 69, a silicon oxide film 73 and a polysilicon film 75.
A field oxide film 71 is formed at the both ends of the main surface of silicon substrate 69. A silicon oxide film 73 is formed between field oxide films 71 on the main surface of silicon substrate 69. A polysilicon film 75 is formed on field oxide film 71 and silicon oxide film 73. An electrode 77 is formed on one end of polysilicon film 75. Electrode 77 and a positive electrode of power source 79 are electrically connected. A negative electrode of power source 79 is grounded.
The resin sealed TEG chip provided with MOS capacitor 67 shown in FIG. 11 and no-resin sealed TEG chip provided with MOS capacitor 67 shown in FIG. 11 were prepared. Electrical stresses were applied to the MOS capacitors by continuously flowing constant current to the MOS capacitors formed on these TEG chips to shift flat-band voltages of the MOS capacitors by a fixed amount. The flat-band voltage means a voltage applied to polysilicon film 75 to make potential at an interface of silicon substrate 69 and silicon oxide film 75 equal to potential in silicon substrate 69. If the flat-band voltage of a semiconductor element shifts, electrical characteristics of the semiconductor element are degraded.
The times required for shifting the flat-band voltage were measured with respect to constant current densities of 10 pA/cm.sup.2, 20 pA/cm.sup.2 and 40 pA/cm.sup.2, respectively. The amount of the flat-band voltage shift is always the same in all cases.
The constant current density designates a value found out by dividing the value of constant current by the area of a portion existing on silicon oxide film 73 of polysilicon electrode 75 shown in FIG. 11. The time required for shifting a certain amount of flat-band voltage of the MOS capacitor of no-resin sealed TEG chip with constant current density of 10 pA/cm.sup.2 is assumed to be 100.
FIG. 12 is a graph showing the results. The broken line shows the test results of a MOS capacitor of no-resin sealed TEG chip and the solid line shows test results of the MOS capacitor of a resin sealed TEG chip. As shown in FIG. 12, excepting the constant current density of 40 pA/cm.sup.2, the MOS capacitor of the no-resin sealed TEG chip requires a longer time period for shifting the flat-band voltage than the MOS capacitor of the resin sealed TEG chip. As described above, shifting of the flat-band voltage causes degradation of electrical characteristics of a semiconductor element. Accordingly, resin seal of a semiconductor chip facilitates electric characteristic degradation of a semiconductor element.
Some semiconductor devices have elements formed on end portions of main surfaces of semiconductor substrates. The element formed on end portions of main surfaces of the semiconductor substrates will be described referring to FIGS. 13 and 14.
FIG. 13 is a partial plan view of a semiconductor device having elements formed on the end portion of the main surface of the semiconductor substrate. Silicon substrate 43 is affixed to die pad 45. A plurality of MOS field effect transistors 55 are formed on the main surface of silicon substrate 43. Bonding pads 47 are also formed on the main surface of silicon substrate 43. There are external leads 51 around a side portion of silicon substrate 43. External lead 51 and bonding pad 47 are electrically connected by wire 49. Silicon substrate 43 is encapsulated with resin 53.
FIG. 14 is a sectional view of FIG. 13 taken along the direction designated by the arrow A. Silicon substrate 43 is affixed to die pad 45. A field oxide film 57 and a gate oxide film 59 are formed on the main surface of silicon substrate 43. Gate oxide film 59 is interposed between field oxide films 57. Gate electrode 61 is formed on gate oxide film 59. An interlayer insulating film 63 is formed on gate electrode 61. A passivation film 65 is formed on interlayer insulating film 63. Silicon substrate 43 is sealed with resin 53 A semiconductor device having elements formed on the end portion of the main surface of the semiconductor substrate includes one illustrated in IEEE (The Institute of Electrical and Electronics Engineers)/IRPS (International Reliability Physics Society) 23rd, 1985, p. 230.
Now, with respect to a resin sealed semiconductor device, it is known that electrical characteristic degradation advances faster in elements formed on end portions of a main surface of a semiconductor substrate than elements formed on a center portion of the main surface of the semiconductor substrate. It seems that this occurs because of the following reasons. Referring to FIG. 14, mechanical stresses due to the resin seal are applied from top, bottom and side directions of silicon substrate 43. The arrows indicate directions of the mechanical stresses. The magnitude of the mechanical stress downwardly (in the top direction) applied to an element formed in the central portion of the main surface of silicon substrate 43 is equal to the magnitude of the mechanical stress downwardly applied to an element formed in the end portion of the main surface of silicon substrate 43. The magnitude of the mechanical stress upwardly (in the bottom direction) applied to an element formed in the central portion of the main surface of silicon substrate 43 is equal to the magnitude of the mechanical stress upwardly applied to an element formed in the end portion of the main surface of silicon substrate 43. However, the magnitude of the mechanical stress laterally (in the side direction) applied to an element formed in an end portion of the main surface of silicon substrate 43 is larger than the magnitude of the mechanical stress laterally applied to an element formed in the central portion of the main surface of silicon substrate 43. Accordingly, larger mechanical stresses are applied to an element formed in an end portion of the surface of silicon substrate 43 than an element formed in the central portion of the main surface of silicon substrate 43. Thus, the electric characteristic of an element formed in an end portion of the main surface of silicon substrate 43 is degraded faster than an element formed in the central portion of the main surface of silicon substrate 43.
Especially, in elements formed at positions located within 100 .mu.m from a perimeter of a main surface of a silicon substrate are liable to electrical characteristic degradation due to mechanical stresses. Semiconductor devices are highly integrated, so that elements are formed even at portions located within 100 .mu.m from the perimeter of the main surface of the silicon substrate. Thus, the problem of electrical characteristic degradation of semiconductor elements due to mechanical stresses can not be neglected.
A TEG chip having elements formed on end portions of a main surface of a semiconductor substrate is now actually manufactured. For example, a TEG chip having elements formed in end portions of a main surface of a semiconductor substrate is disclosed in the "Solid-State Electronics" Vol. 21, pp. 1045. However, what is disclosed in this document is not a TEG chip itself, but a mask pattern. FIG. 15 is a plan view of a mask pattern 81 disclosed in "Solid-State Electronics" Vol. 21, pp. 1045. Mask pattern 81 will be regarded as a TEG chip 81 in the following. A large number of diodes are formed in TEG chip 81. The diodes located at symmetrical positions about an axis line 95 have the same shapes and areas but formed of different materials. For example, diode 82 is formed in polysilicon layer 87. Polysilicon layer 87 and bonding pad 83 are electrically connected by interconnection layer 85.
Diode 94 is formed in an epitaxial layer 93. Epitaxial layer 93 and bonding pad 89 are electrically connected by interconnection layer 91. Diode 82 and diode 94 are located at symmetrical positions about axix line 95.
However, in TEG chip 81 shown in FIG. 15, the elements were not formed on end portions in consideration of the fact that elements in the end portion are supplied with larger mechanical stresses.
Furthermore, as a plurality of TEG chips are manufactured out of a piece of a wafer, a plurality of electronic elements having the same types, dimensions and materials were not formed in a single TEG chip. Accordingly, in a conventional TEG chip, a comparison could not be made between electronic elements with the same types, dimensions and materials formed at positions where different amounts of mechanical stresses are applied to.